A prior art differential voltage sensing memory is shown in FIG. 1. Memory 100 includes memory cells 101, 102. . . ,10n. The memory cells are connected to precharging circuit 110, write circuit 120, and sense amplifier circuit 130 through bit lines 141 and 142. Bit line 142 provides a signal that is the complement of the signal on bit line 141. Each memory cell has pass gates 15n and 16n, which are connected to word lines 17n. When the word line for a given cell, such as cell 101 for example, is high, a differential voltage is generated on bit lines 141 and 142. The sense amplifier circuit 130 reads the data stored in the cell 10n by detecting the differential voltage, and provides an output indicating the value of the data stored in the memory cell 101.
Thus, sense amplifier 130 needs two bit lines 141, 142 to generate a differential voltage in order to read data from a given cell 10n. The overhead from the sensing circuit in the conventional symmetrical memory is rather large, which prevents the use of this memory in high performance devices that cannot devote this large amount of space to the sensing circuitry required for detecting a differential voltage. Therefore the prior art memory cannot provide microprocessors with a large on-chip cache memory having both high speed and reduced area.
Another disadvantage of the prior art memory cells is that the memory cell circuit has to be symmetrical, which requires identical transistors and bit lines on both sides of the memory cell and related sensing circuitry. Therefore, the transistors in the left and right side of the prior art memory cell have to match within very narrow error margins. As the technology scaling continues to decrease, the mismatch in symmetry of the transistors of the memory cell become worse due to manufacturing process variations. It becomes more difficult for the manufacturing processes to decrease the size of the transistors and maintain transistor symmetry within acceptable error margins. Therefore, it is extremely difficult to maintain both cell stability and high sensing speed in the conventional small signal, differential voltage memory circuits.